What is special about gateware?

As described in the Best Practices for Sharing FPGA Designs published by OSHWA, the Open Source Hardware Association, gateware -- code written in Hardware Description Languages (HDL) -- has a dual nature: it behaves as software when you feed it to a simulator running in a computer and it behaves as hardware design files when you use it as a base for the design of an Application-Specific Integrated Circuit (ASIC). Gateware can also be used to configure a heterogeneous reconfigurable target such as an Field-Programmable Gate Arrays (FPGA), a Complex Programmable Logic Device (CPLD) or a System-on-Chip (SoC).

To make the border between gateware and software even more blurry, nowadays you can even use traditional software programming languages like C++ and Python to design hardware.

In recent years, gateware design has seen a great boost in designer productivity by embracing best practices from the software world. In particular, it is now customary to include continuous integration and continuous deployment (CI/CD) as part of the standard HDL design flow. Compared with software, one big difference is that many of the most widely-used tools for simulation and logic synthesis are proprietary. This means that particular care has to be devoted to preparing the CI/CD pipelines in the collaboration platform (GitHub, GitLab...) because most of the End-User Licence Agreements (EULA) you or your institute have signed with the vendors of the proprietary tools do not allow you to grant access to the tools to any of your external collaborators. See the dedicated how-to guide on this subject for guidance on how to set up CI/CD for gateware at CERN.