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A flow to design, produce and test Printed Circuit Boards (PCB) at CERN

The figure below shows a possible flow for PCB design at CERN, including production and testing considerations. Notice that, even if you use a different flow, a CERN OSHW design is expected to have all the intermediate and final deliverables described here.

Here is a quick description of the different phases:

  1. Following a requirements gathering and informal brainstorming phase, the first visible deliverables are the functional specification and the validation plan. The former answers the question "what does the hardware need to do?" and the latter provides clarity on how the resulting hardware will be tested against this specification.
  2. The Preliminary Design Review (PDR) validates these two documents.
  3. The next phase deals with schematics. The deliverables here are the schematics themselves and a design document explaining the rationale behind the main design choices. This document helps the review process and also is a key part of the communication of the designer with future designers or with his/her future self.
  4. The Conceptual Design Review (CDR) validates the schematics and the design document. See one example of schematics review checklist used in the BE-CEM-EDL section at CERN. There are many other good checklists out there.
  5. Place and route is the next phase. At CERN, this is typically done by the PCB Design Office. At the same time, the designers already have the detailed knowledge of the design at this stage, which they need to turn the initial validation plan into a more concrete test plan.
  6. Both the layout and the test plan are reviewed during the Final Design Review (FDR).
  7. Following a successful FDR, prototypes can be ordered, and the Production Test System (PTS) can be validated using them.
  8. After successful validation of prototypes, a Production Readiness Review (PRR) ensures all conditions are met to launch series production. See here one example of PRR criteria used in BE-CEM-EDL.

The above procedure is of course iterative. It is very common to find issues during the layout review that affect the schematics, and the tests of the prototypes often take us back to schematics as well. The iterations happen until all the conditions in the PRR are met.